1. Field of the Invention
The present invention relates to a level shifting circuit and to an active matrix driver including such a circuit.
2. Description of the Related Art
Level shifting circuits are required, for example, in digital metal oxide semiconductor (MOS) circuits which are required to respond to input signals of substantially lower amplitude than the supply voltage. Such circuits are used in silicon-on-insulator (SOI) circuits which are required to interface with low voltage signals, for example having amplitudes typically in the region of from 1 to 5 volts, but which typically operate at substantially higher supply voltages, for example in the region of between 10 and 20 volts. A specific example of such an arrangement is a monolithic driver circuit for a flat panel active matrix display fabricated with poly-silicon thin-film transistors (TFTs). Another application of level shifting circuits is in interfaces between different logic families, for example TTL and CMOS.
FIG. 1 of the accompanying drawings illustrates a known type of level shifting circuit comprising n-channel transistors 1 and 2 whose sources are connected to ground and whose drains are connected to the drains of p-channel transistors 3 and 4, respectively. The sources of the transistors 3 and 4 are connected to the drains of p-channel transistors 5 and 6, respectively, whose sources are connected to a power supply line vdd. The drains of the transistors 1 and 3 are connected to the gate of the transistor 6 and to a complementary output !OUT whereas the drains of the transistors 2 and 4 are connected to the gate of the transistor 5 and to an output OUT. The gates of the transistors 1 and 3 are connected to an input IN whereas the gates of the transistors 2 and 4 are connected to a complementary input !IN.
Although such an arrangement is capable of providing level shifting of a digital input signal such that the output voltage swing is greater than the input voltage swing, this arrangement is not tolerant of transistors with threshold voltages which are of a similar level to the input signal. For example, poly-silicon transistors may have a threshold in the region of 3 volts and so such a circuit can only operate with input signals having a higher level substantially greater than this with respect to ground.
FIG. 2 of the accompanying drawings illustrates another known level shifting circuit which is more tolerant of high transistor threshold voltages. This type of arrangement is known as a differential current mirror sense amplifier and is disclosed, for example, in N.West and K.Eshragian, xe2x80x9cPrincipal of CMOS Designxe2x80x9d, Addison Wesly, 1993. The circuit comprises a differential pair of n-channel transistors 7 and 8 whose gates are connected to complementary input terminals INB and IN, respectively, and whose sources are connected to a tail current source comprising an n-channel transistor 9 whose gate is connected to a bias voltage source Vbias and whose source is connected to a power supply line vss. The drains of the transistors 7 and 8 are connected to a current mirror formed by p-channel transistors 10 and 11 connected to a further supply line vddd and the drain of the transistor 7 forms the output OUT of the circuit. However, this type of circuit is unable to provide a high degree of level shifting, especially for a digital logic signal where one logic level remains unshifted.
U.S. Pat. No. 5,729,154 discloses another known type of level shifter which is more suitable for poly-silicon integration technology and which is illustrated in FIG. 3 of the accompanying drawings. The circuit comprises an n-channel transistor 12 whose source is connected to an input IN and whose drain is connected to the drain of a p-channel transistor 13, whose source is connected to a supply line vddd. Another n-channel transistor 14 has a source connected to a supply line vss and a gate and drain connected together and to the gate of the transistor 12 and to the drain of a p-channel transistor 15, whose source is connected to the supply line vddd. The gates of the transistor 13 and 15 are connected to the supply line vss. The drains of the transistors 12 and 13 are connected to a conventional complementary transistor inverter comprising transistors 16 and 17 and whose output forms the output OUT of the level shifting circuit.
A disadvantage of this arrangement is that it has a relatively high current consumption. In particular, the transistors 14 and 15 form a path between the supply lines vddd and vss which conducts current continuously. Also, when the input signal to the source of the transistor 12 is a logic low level signal, there is a further path through the transistors 12 and 13 between the supply lines. In order to avoid phase delays between the input and the output signals of the level shifting circuit, the circuit must operate at high speed. This requires relatively large currents and results in a relatively large power consumption.
GB 2 360 405 discloses level shifting circuits which are capable of operating at high speed and with relatively low power consumption. FIG. 4 of the accompanying drawings illustrates one example of such a circuit which comprises an n-channel transistor 18 and a p-channel transistor 19. The source and gate of the transistor 18 are connected to a signal input IN and an enable input EN, respectively, whereas the drain of the transistor 18 is connected to an output terminal OUT. The transistor 19 has a gate connected to a supply line vss, a source connected to another supply line vddd and a drain connected to the output terminal OUT.
When the enable signal at the enable input EN is active, the gate of the transistor 18 is biased to a voltage higher than its threshold voltage relative to the supply line vss. The transistor 19 is biased so as to be on but is more xe2x80x9cweaklyxe2x80x9d conductive than the transistor 18. When the input signal at the input IN is at a low level (at or near the potential of the supply line vss), the transistor 18 is turned on and conducts more strongly than the transistor 19 so that the output is pulled to a low level. Conversely, when the input signal is at a higher level, the transistor 18 is turned off and the output OUT is pulled towards the voltage of the supply line vddd by the transistor 19. When the circuit is disabled, the transistor 18 is turned off and the output OUT is pulled towards the voltage of the supply line vddd by the transistor 19.
FIG. 5 of the accompanying drawings illustrates a modified form of the level shifting circuit shown in FIG. 4 in which the enable input EN is also connected to the input of an inverter 20 whose output is connected to the gate of the transistor 19 and to a pull-down transistor 21. In this case, when the circuit is disabled, the transistor 19 is switched off and the pull-down transistor 21 pulls the output OUT towards the voltage of the supply line vss.
FIG. 6 of the accompanying drawings shows another form of the level shifting circuit of GB 2 360 405. The gate of the transistor 18 is connected to the gate and drain of an n-channel transistor 22 whose source is connected to the supply line vss. The source and drain of the transistor 22 are connected to the drain of a p-channel transistor 23 whose source is connected to the supply line vddd and whose gate is connected to the gate of the transistor 19 and to the enable input EN. The enable input EN is connected to the gate of the pull-down transistor 21 and to the gate of another pull-down transistor 24 connected across the transistor 22.
This arrangement provides more accurate biasing of the xe2x80x9cpass gatexe2x80x9d transistor 18 and provides a higher degree of level shifting. When the circuit is enabled, the transistors 22 and 23 bias the gate of the transistor 18 just above its threshold voltage. When the circuit is disabled, the pull-down transistor 24 is turned on and the gates of the transistors 18 and 22 are pulled towards the voltage of the supply line vss so that the transistors are switched off.
There are many applications in which the input signals whose voltage levels are to be shifted have a relatively small mark:space ratio (MSR) and the synchronisation requirements are such that only one edge of the input signal needs to have its timing maintained accurately. For example, one such application is in active matrix display in which such circuits are used to shift the levels of vertical and horizontal synchronisation signals as illustrated in FIG. 7. Although the level shifting circuits disclosed in GB 2 360 405 provide good performance, they may not provide an optimum solution because it is necessary for such circuits to be permanently enabled in order to respond to the incoming synchronisation pulses.
U.S. Pat. No. 6,268,755 discloses a MOSFET predrive circuit with independent control of the output voltage rise and fall times. This circuit comprises a first voltage level shifting circuit for converting an input signal having a first voltage swing to an output voltage having a second voltage swing and a second stage for controlling the rise and fall times of the output signal.
U.S. Pat. No. 6,087,881 discloses an integrated circuit level shifting predrive circuit having two level shifting stages which are connected in series. This level shifting circuit uses three bias supply circuits, each providing a different DC bias voltage. A first stage shifts the input signal voltage from the lowest bias voltage to the intermediate bias voltage. A second stage shifts the signal voltage from the intermediate bias voltage to the highest bias voltage. This arrangement distributes the voltage swing among the devices such that the stress across the dielectric layer of any single device is reduced.
With the above-described conventional structure, in order to avoid phase delays between the input and the output signals of the level shifting circuit, the circuit must operate at high speed. This requires relatively large currents and results in a relatively large power consumption.
The present invention has an objective of providing a level shifting circuit which solves the above-described problems, and is capable of operation at high speed and is of relatively low power consumption as compared with the above-described conventional art, and an active matrix driver using the same.
According to a first aspect of the invention, there is provided a level shifting circuit comprising: a first level shifting stage having a first enable input, a first signal input for receiving an input signal having a first voltage swing, a first output for providing a first output signal having a second voltage swing greater than the first voltage swing, a first power consumption when enabled, and a first switching speed; and a second level switching stage having a second enable input connected to the first output, a second signal input for receiving the input signal, a second output for providing a second output signal having a third voltage swing greater than the first voltage swing, a second power consumption when enabled and a third power consumption when disabled with the second power consumption being greater than each of the first and third power consumptions, and a second switching speed which is faster than the first switching speed.
The term xe2x80x9cvoltage swingxe2x80x9d as used herein means the difference between the maximum and minimum voltages of a signal. The term xe2x80x9cswitching speedxe2x80x9d as used herein refers to the reciprocal of the time taken for a signal to switch between its extreme values within predetermined tolerances.
The input signal may swing between first and second voltage levels and the first and second stages may be arranged to shift only the second voltage level. The first voltage level may be ground potential.
The third power consumption may be substantially equal to zero.
The second stage may comprise setting means for setting the second output to a predetermined state (for example high level, low level or high impedance) when the second stage is disabled. The setting means may comprise a pull-up or pull-down transistor whose control electrode is connected to the second enable input.
The first enable input may be connected for permanently enabling the first stage.
The first and second signal inputs may be differential inputs.
The circuit may comprise a sequential logic circuit having a synchronisation input connected to the second output and a clock input for receiving a clock signal. The logic circuit may be arranged to produce output pulses synchronised to the second output signal and to the clock signal. Each output pulse may have a pulse width substantially equal to the pulse width or period of the clock signal.
The logic circuit may comprise a D-type latch having a data input connected to the second output and a clock input connected to receive the clock signals. The logic circuit may comprise an AND gate having a first input connected to the second output and a second input connected to an inverting output of the latch.
The circuit may comprise a third level shifting stage having a third output connected to the clock input of the logic circuit, a third signal input for receiving the clock signal, and a third enable input responsive to the second output signal. The third enable input may be connected to the second output.
As an alternative, the third enable input may be arranged to receive the result of ANDing the second output signal with the complement of the output signal of the logic circuit.
Each of the first and second stages and the third stage when present may comprise a sub-stage comprising a first transistor of a first conductivity type whose common terminal is connected to the signal input of the stage and whose output terminal is connected to the output terminal of a second transistor of a second conductivity type opposite the first type, whose common terminal is connected to a first power supply line. The output terminal of the first transistor may be connected via at least one inverter to the output of the stage. The control terminal of the first transistor may be connected to the enable input of the stage. The control terminal of the second transistor may be connected to a second power supply line.
The sub-stage may comprise a third transistor of the first conductivity type, whose control and output terminals are connected to the control terminal of the first transistor, and a fourth transistor of the second conductivity type, whose common terminal is connected to the first power supply line, whose output terminal is connected to the output terminal of the third transistor, and whose control terminal is connected to the control terminal of the second transistor and to the enable input of the stage. The common terminal of the third transistor may be connected to a second power supply line. In the case of complementary signal inputs, the common terminal of the third transistor may be connected to a complementary signal input of the stage.
The sub-stage of each of the second stage and, when present, the third stage may comprise a pull-down transistor connected between the output terminal of the first transistor and a or the second power supply line with a control terminal connected to the second or third enable input.
The terminology used herein to refer generically to the terminals of a transistor is such that the common terminal and the output terminal are connected to the main conduction path through the transistor and the voltage between the control and common terminals or the current flowing between the control and common terminals controls the conduction of the main conduction path between the common and output terminals. In the case of field effect transistors, the common terminal is the source terminal, the output terminal is the drain terminal, and the control terminal is the gate terminal.
The or each transistor may be a metal oxide semiconductor (MOS) transistor, for example a poly-silicon thin film transistor.
According to a second aspect of the invention, there is provided an active matrix driver comprising a circuit according to the first aspect of the invention.
It is thus possible to provide a level shifting circuit which is capable of operation at high speed and is of relatively low power consumption. Such an arrangement is particularly suitable for level-shifting signals of small mark: space ratio because the second stage is enabled with a relatively low duty cycle. The relatively high power consumption of the second stage only occurs when necessary and the first stage is not required to operate at such high speed and can therefore have a much lower power consumption. This arrangement is particularly suitable where the input signals are pulses and synchronisation to only one edge of each pulse is required.
A further advantage of such a circuit is that, when embodied by MOS transistors, the degradation over time of the gate dielectric of individual devices due to hot electron and other effects, such as oxide charging, is reduced. The first stage of the circuit has a relatively low current consumption. The second stage has a higher current consumption, but the devices of this stage have substantially reduced on-time. The strain on any single device is therefore reduced.
Such a level shifting circuit provides a low power consumption arrangement for producing signals which are, for example, of direct use as control signals in an active matrix driver.